Karakoc, M.C.Kirkaya, E.Ersoy, O.Sanli, M.Çiçek, A.Cavus, E.Gülden, M.A.2026-03-262026-03-262018978153861501010.1109/SIU.2018.84046942-s2.0-85050800083https://doi.org/10.1109/SIU.2018.8404694https://hdl.handle.net/20.500.14901/3808Aselsan; et al.; Huawei; IEEE Signal Processing Society; IEEE Turkey Section; NetasIn this work, after some of the commonly used symbol timing synchronization algorithms used in orthogonal frequency division multiplexing systems are examined, a two-step (coarse and fine) symbol time offset (STO) correction algorithm based on Schmidl & Cox [1] approach is investigated in Simulink model. Subsequently, relying on this Simulink model, the STO algorithm is implemented on ZYNQ ZC706 XC7Z045 FPGA working fully parallel at a clock rate of 200 MHz. The implementation results are compared with the other related studies in the literature. © 2018 IEEE.trinfo:eu-repo/semantics/closedAccessFPGAOFDMSToConference Object